Simulation in verilog using $monitor -

Simulation in verilog using $monitor -

i've been trying implement total adder in verilog. have implemented , showing results on isim. problem when seek see simulation using $monitor command, showing me 1 result, not simulation results. here testbench code:

module full_adder_s2_testbench; // inputs reg a; reg b; reg cin; // outputs wire sum; wire cout; // instantiate unit under test (uut) full_adder_s2 uut ( .a(a), .b(b), .cin(cin), .sum(sum), .cout(cout) ); integer i; initial begin // initialize inputs = 0; b = 0; cin = 0; // wait 100 ns global reset finish #100; end @ ( a, b, cin ) begin // generate truth table ( = 0; < 8; = + 1 ) // every 10 ns set a, b, , cin binary rep. of #10 {a, b, cin} = i; $monitor( "%d ns: + b + cin = %b + %b + %b = cout sum = %b %b", $time, a, b, cin, cout, sum ); // stop 10ns after lastly alter of inputs #10 $stop; end endmodule

and here result in isim:

run 1000 ns

simulator doing circuit initialization process.

finished circuit initialization process.

400 ns: + b + cin = 1 + 1 + 1 = cout sum = 1 1

stopped @ time : 410 ns : in file "e:/namal/fyp/my work/xilinx/full_adder_s2/full_adder_s2_testbench.v" line 66

$monitor meant setup 1 time , trigger every time signal changes, seek using $display since have statement within of always @*.

while learning verilog encourage utilize begin end liberally. issue 1 line in loop, $display/$monitor outside , executed 1 time @ start.

always @* begin // generate truth table ( = 0; < 8; = + 1 ) begin //<-- added begin // every 10 ns set a, b, , cin binary rep. of #10 {a, b, cin} = i; $display( "%d ns: + b + cin = %b + %b + %b = cout sum = %b %b", $time, a, b, cin, cout, sum ); end //<--added end // stop 10ns after lastly input #10 $stop;

end

full illustration on eda playground.

nb: best not utilize manual sensitivity lists more replace always @ ( a, b, cin ) always @*. result in quicker refactoring , lowering chance of rtl gates simulation mismatch.

simulation verilog